MEMORANDUM

 

To:           Katalin Voros, Operations Manager

From:          Sia Parsa, Process Engineering Manager

Subject:      2006 Year-End Report

Date:          12 January 2007

 

 

I.     OVERVIEW

As part of the management team in the Microlab, I supervise the process engineering unit comprised of 4 process engineers, including the MEMS-Exchange engineer, one baseline research associate and average of three lab assistants (students). 

This memorandum documents process engineering activities for the calendar year 2006. Faced with new challenges this past year, "post 6" upgrade", staff had to work harder and smarter to ensure continued smooth operation in the Microlab. A great team work and good planning rendered our ASML 5500/90  DUV stepper operational with a new (donated used) Cymer laser (5600 model), which replaced an unsupportable/deteriorating laser (Cymer 4600D model) on this particular stepper.  Also, for the second year in a row, process group managed to offer double the number of our usual Engineering Test Request (ETR) services. A broader range of processes were offered through this revenue generating program, while keeping up with another processing service through MEMS-Exchange program not to exclude, the baseline activity, which also generated some revenue for the Microlab. The second baseline run was completed using a modified version of the 0.35΅m process. It successfully met our objectives both in terms of electrical parameter optimization and fabrication of new MEMS structures/IC circuitries; we are currently working on the final report. Other activities included: solving process problems in the lab, support of the EE143 lab, performing special ETR requests, mask making service, process equipment monitoring, manual updating, grading tests, and many other activities required to  ensure smooth operations in the Microlab and fulfillment of its obligations to the scientific community  on/off campus.

The following summarizes Process Engineering activities for the calendar year 2006.

II.   EQUIPMENT UPGRADE & NEW INSTALLATIONS

Laser upgrade (New Cymer 5600 On ASML)

A new 5600 model Cymer laser replaced our old dying laser (Cymer 4600D model). This was a major upgrade and totally unknown how our ASML 5500/90 will function with a more advanced laser model that was really designed for a newer generation of ASML steppers. We were very concerned that the older stepper will not talk to the newer Cymer laser. A good decision was made by the management to first bring up the new laser on its own, then have it connected/tested on the ASML stepper. This allowed equipment engineer Evan Stateler to patiently/thoroughly evaluate the new laser, seek Cymer field engineer's support and successfully fire up the system as an independent module. Once this was done, the old laser was moved out of its position, replaced by the new one. We then proceeded with ironing out the last communication and operational issues on the new set up.  Process staff performed the necessary test/set up routines before releasing the tool to members on July 12th, 2006. Since then, equipment and process staff have worked closely together to implement necessary procedures that have adequately met stepper/laser compatibility issues, making the operation transparent to the end users. As a result of these actions, we now have a much more reliable stepper with better uptime, and incredibly faster stepper exposure speed than before the upgrade.

GCAWS2 Computer Upgrade

A new computer (PC) replaced the old DEC PDP, which had parts/support issues. The transition to the new computer was relatively smooth. Process staff conducted two training sessions, and set up new stepper jobs for current members in Oct, 2006. The old 5 1/4- inch floppies were phased out, replaced by  3 1/2-inch 1.44 MB floppies, supported by  the new PC.

Sopra Ellipsometric Computer Upgrade

A new computer and applicable hardware (PC, IOP2 board, and switch box) plus a newer version of the software (Windows XP based Winelli, Gespak  & Getest) was installed and configured on the Sopra machine. This was in response to limited multitask capability of the old computer/software pointed out by Microlab members (computer lock up, when acquisition software, as well as any other applications were running at the same time). After the upgrade, all of our current recipes, parameter files, structures and data points from the old computer were successfully copied over to the new computer system. Calibration of Sopra was performed and the upgrade was validated by taking SOPRA reference sample measurements.

III.      PROCESS DEVELOPMENt, sustaining & IMPROVEMENT ACTIVITIES

Mix&Match  Lithography

This year the Mix & Match scheme for deep submicron lithography was instituted in the Microlab (report submitted on 12/06). This procedure enables members make efficient use of both ASML and GCAWS6 steppers together to meet their submicron lithography needs. Members can use the new ASML and GCAWS6 templates for their CAD layout design/mask making, hence assign a particular layer to stepper of choice based on its resolution and registration requirements. The most logical choice for the best resolution and alignment accuracy in our case would be to keep critical layers on the ASML 5500/90 stepper (DUV), while non-critical layers are addressed by the GCA stepper (I-line). This methodology can only be applied to new run/s, as both the ASML pre-alignment (PM) marks and the GCAWS6 global alignment marks are needed for successful exposure of all lithography layers in a process run.

ASML 5500/90

ASML continues to play an important role in addressing high end lithography needs of the device group, LBL, BMLA, as well as MEMS research groups in the Microlab. This year we grew more independent of ASML support by resolving stepper problems, and performing some of the field support procedures on our own.  Image quality control (IQC) feature, which was locked up by the stepper in late November was quickly identified as laser problem, and later resolved by performing F2 injection on the laser side. Once the stepper allowed us to perform the IQC test, we then brought the pertinent parameters under control. This was achieved by performing the necessary field engineering procedures on the stepper. Some of these procedures (routines) are tedious and time consuming, others need special tools and are best left to ASML field engineer. This particular case, however was straight forward, so I performed the "stone to lens height/tilt" followed by "white level sensor height/tilt" to zero out the stage tilt, and center the focal plane (2 days work). "Red and blue" test was also performed by staff to correct for X&Y stage drift, hence minimizing layer to layer registration error (1/2 day work). We also included the laser inject to the list of our regular maintenance for the ASML stepper.   

ASML field engineer replaced the barcode reader assembly library in the stepper reticle management unit, as well as performing quarterly maintenance in November 2006.

New Process Recipes/ Stepper jobs

A.      New HTO and TEOS Trench Fill Processes

Preliminary work has been done towards developing a much faster “High Temperature Oxide” (HTO) disposition process for both theTystar9 and Tystar17 furnaces. This work is in progress and the initial data has been very promising.  HTO films at 2-3 times faster rate were deposited in Tystar9 by the new version of the HTO process.  We also had good results on a trench fill TEOS process (P-5000 AMAT machine). A series of deposition and etch steps have enabled us to fill high aspect ratio (~6:1) submicron trenches (W = 0.35 ΅m, depth = 2 ΅m). These projects were carried out by Jimmy Change. Please, see his report for more detail.

B.      Edwards Sputtering Recipes

Edwards sputtering data generated by Daniel Queen (Ph.D. candidate) and his undergraduate associates, as well as his collaborative study on sputtered film resistance with our two high school interns (Andrea Imhof/Sonia Ganju) in the summer, were included in the Edwards sputter coater manual on the web.

Standard Processes (Edwards Machine)

Material

Magnetron Gun Type

Power (W)

Pressure (MTorr)

Rate (A/min)

Cr

RF

100

6.5

38

Ti

RF

100

5

20

Al

DC

300

5

182

Cu

DC

300

5

248

Au

DC

200

5.5

277

Pt

DC

300

5

198

Low Film Stress Processes (Edwards machine)

Material

Magnetron Gun Type

Power (W)

Pressure (MTorr)

Rate (A/min)

Film Stress

Pt

DC

300

8

200

16.5 MPa, tensile

Cu

DC

100

2

106

218 MPa, compressive

Cr

DC

300

0.4

189

53.4 MPa,  tensile

C.      New Stepper Jobs

New stepper jobs for ASML and GCAWS2, GCAWS6 steppers were generated. A 9-image special application job was generated for one of our optoelectronics researchers (small dies). All nine lithography layers needed for this particular case were effectively combined onto the same CAD layout (one mask), therefore, a great saving in the fabrication of the required high resolution mask was realized (A sub-half micron resolution mask can costs anywhere between $1500 -$2500, 8X saving). 

Process & Equipment Issues

Tystar16 Furnace

This year we experienced particle problems in Tystar16, our Non-MOS poly furnace in the Microlab. This problem was attributed to premature silane decomposition caused by a hot spot in the furnace profile, N2-vac MFC and venting procedure problems. This problem was clearly identified through some test trials performed by our process staff (Jimmy). Particle issues were later resolved by fixing the heater element problem (better temp profile), and through implementation of a soft pump (shunt) and changing the N2 Vac MFC to a normally closed type. Please note, we previously used normally open MFC, which increased the chance of particles getting pushed back into furnace at the start of the deposition step. These modifications have prevented particle generation, as well as particle migration from back/exhaust portion of the furnace (dirty side) into the process chamber (quartz tube) during deposition and venting steps. Equipment staff and the Machine shop played a crucial role in implementing these corrective measures, which have resulted in improved poly film quality/reduced particles in the Tystar16 furnace.

Lab Manual Write-Up, Process Monitoring, & Qualification Test

This year, staff managed to update just about all of our on-line equipment manuals, no date later than 3 years old can be seen on any of the manuals. As always, process staff, BSAC engineer and a selected number of Microlab members took part in accomplishing this task, which also included posting new manuals for the upgraded/new tools online.

New and Rewritten Manual

Chapter 5.36   -  New manual for YES vacuum oven was posted online 6/06)

Chapter 8.05   -  New (total rewrite) manual was posted for Electroglas Autoprobe station. The

                                    PC windows based program (recommended) called Metrics I/CV was offered as a primary mode of operation. The second, older

                                    method Sunbase3 program (Unix based codes), was also included in the manual, appendix section (10/06)

Chapter 8.22   -  New manual for linewidth measuring system was posted (6/06)

Chapter 8.24   -  New manual for Memscope was posted (5/06)

Chapter 10.2   -  New manual for post CMP clean process, included SRD operation (12/06)

Updated Manual Chapters

Chapter 3.3    -  Updated GCA 3600F Pattern Generator section 3.0  (7/06).

Chapter 3.4    -  Updated APT Emulsion manual, scope and some develop parameters (12/06).

Chapter 5.2    -  Added link to Process Monitoring and modified cleaning procedure (8/06).

Chapter 5.3    -  Added link to Process Monitoring and modified cleaning procedure (8/06).

Chapter 5.4    -  Added link to Process Monitoring and modified cleaning procedure (8/06).

Chapter 5.10   -  Minor changes to section 5.0 of tystar10, process terminology (8/06).

Chapter 5.12   -  Minor changes to section 5.0 of Tystar12 manual, process terminology (8/06).

Chapter 5.15   -  Updated Tystar15 manual, process terminology (8/06).

Chapter 5.19   -  Modified sections relating to the new BCl3 source and new recipes (12/06).

Chapter 5.31   -  Update Heatpulse1/2 manual, scope and other sections (01/06).

Chapter 5.35   -  Update Nanox furnace manual (5/06).

Chapter 6.01   -  Minor update of the Hummer sputter manual, new location (12/06)

Chapter 6.04   -  Added cross contamination warning (pallets) to CPA manual (03/06)

Chapter 6.07   -  Updated the Edwards manual with standard and low film stress process parameters,

                        also defined cut off value for power in this tool (10/06)

Chapter 7.1    -  Updated lam1 manual with additional process notes (2/06)

Chapter 7.2    -  Updated lam2 manual with additional process notes (2/06)

Chapter 7.3    -  Updated lam3 manual with additional process notes (2/06)

Chapter 7.4    -  Updated lam4 manual with electrode temperature problem/solution (11/06)

Chapter 7.5    -  Updated lam5 manual with electrode temperature problem/solution (11/06)

Chapter 7.9    -  Updated P-Therm current gas list and associated fields in the manual (4/06)

Chapter 7.15   -  Updated Added PID calibrated parameter table to HF-vapor manual (4/06)

Chapter 8.34   -  Updated Nanometrics manual with special UV program instruction (5/06)

Process Monitoring & Equipment Qualification Test 

Our student helpers have done a great job attending to required wafer dummies at the stations, cleaning boats in furnaces and timely execution of process monitors on our baseline tools. Jimmy has managed their activities in the lab, also provided support/training for the new students hire. He also interfaced with the IT group to maintain our database and the process monitoring website: http://microlab2.eecs.berkeley.edu/ProcessMonitor/index.html

A large number of equipment qualification, written and/or oral equipment tests were given by staff this past year. Process group, BSAC and the baseline engineers provided additional training on some of our high end tools in the lithography, etch, CAD layout and mask making areas. Many more members are now qualified on ASML, CMP, Centura MxP+ / DPS-DT machines.

IV.          process Staff Supervision, TRAINING & OTHER SERVICES

Staff Supervision:  I continued supervising of 4 process/MEMS-Exchange engineers, one baseline assistant specialist, as well as an average of 3 assistant students working in the process group. Process staff yearly appraisals were submitted on time, before the September 1st 2006 deadline. 

Promotion and Awards: This was a good year for the process group, as one of our engineers, Jimmy Chang was promoted to Senior Development Engineer (09/06), and Marilyn Kushner another engineer in the group received a Spot award (12/06), which is designed to create role models and communicate the type of noteworthy accomplishments that the campus appreciates.

New Student Hire:  Peter Tabada and Tessie Lee joined the process group. The new students along with the old timer, Raza have done a great job performing routine sustaining work and process monitoring on our baseline tools.

High School interns:  High school interns, Andrea Imhof and Sonia Ganju joined us in the summer and went through basic wafer process training, later participated in a very nice project on aluminum metal deposition and resistance uniformity study of deposited aluminum film in Edwards machine. They presented their work result to a Microlab staff audience at the end of the summer.

Microlab, EE143:  Process staff provided services to EE143 lab by ordering new furnace boats, supplying them with their chemical inventory and helping TAs with their poly/oxide runs. 

Advising Other Universities, Institutions:  Held weekly meetings with our technology manager discussing Microlab member special process requests. I also provided help/advise to UCB/LBL colleagues, other Universities and the industry. Last year we assisted Dr. Frank Yaghmaie, Director of Northern California Nanotechnology Center at UC Davis with appropriate test structures/mask for his nano-imprinting project. We helped University of Arizona Micro/Nano Fabrication Center with their process/equipment questions on their Edwards E-beam evaporator. I provided process information for a proposed publication, which followed Dr. Meagley's Self Assembly Monolayer ETR performed in the Microlab during the previous year.  I helped Stanford students in Professor Pease's group, Professor Howe's group, and Professor Khuri-Yakub's group (EE department). We agreed one of our graduates, J. Provine act as liaison and perform Stanford students’ DRIE and other process requests at the UC Berkeley Microlab. I helped the SFSU staff with gas purity information needed for their lab.

V.   Semiconductor Processing & special Services

ETR Services

For the past two years process staff has been able to offer an incredible number of Engineering Test Requests (ETRs), almost double the amount of ETRs performed the previous years.  We successfully completed 27 ETRs with much faster response time generating $56,922.30 in revenue for the Microlab. In addition to the standard processing normally offered in the litho, etch and the diffusion areas, we performed many other types of non-baseline processes, which included; CMP for SRI international, Pd deposition/SEM work for U.S. Naval Postgraduate School, parylene deposition for Medtronic, oxinitride film deposition for a BMLA company, DRIE process for Motorola, and DUV lithography/SEM work for a consulting company.

MEMS-EXCHANGE PROCESS service

This year Microlab continued with providing process services/support to the DARPA sponsored MEMS-Exchange (MX) program. I have been managing the one engineer assigned to the task of processing MX runs at our site. This included holding weekly meeting with MEMS-Exchange engineers to discuss current and future runs, possible processing problems, as well as evaluating and approving run/s for our site. We performed over 80 process steps, which generated ~$50K revenue for the Microlab. One of the highlight of this year's activity was salvaging Professor Lewei Lin’s run, which was referred to us after running into major process problems (DRIE step) at other MX sites. Thanks to a good team effort and valuable advice from our resident DRIE expert, Matt Wasilik, we managed to salvage this run and continued through the remainder of process steps, yielding good MEMS structures at the end. A modified version of the run was submitted to us in December, and recently approved by us for all etch steps, as well as the HF vapor release process at our site, currently awaiting the tape out/start.

Mask Making Services

A total of 1053 new masks were processed on the pattern generator over the course of the past year. We also had some overseas university customers for the first time.

Internal Fabrication Services & Special Requests

VI.      CMOS  Baseline activities

Second Baseline Run  (0.35 ΅m Process)

This year process group successfully completed our second 0.35΅m run, CMOS-170. The main goal of this run was to match threshold voltages (Vt absolute values) of  P-channel and N-channel devices on the test chip. This was achieved by adjusting Vt implant dose from 4e12 cm-2  (CMOS-160, 1st run)  to  3e12 cm-2  (CMOS-170, new run), based on simulation data obtained earlier.  We also reduced our minimum feature size ( transistor gate length) on the CMOS-170 run,  and were able to successfully fabricate 0.3 ΅m NMOS and PMOS devices, which were below the ASML DUV stepper specification limits (CD > 0.35 ΅m). Figures 1 and 2 show a good match between the parametric measurements (Dotted lines) performed on the fabricated devices and the BSIMPro+ simulation results shown as continuous curves. Id Vd and subthreshold characteristics (logarithmic) for N-channel and P-channel devices are shown on these curves for the 0.3 ΅m, minimum size devices. Below table shows the threshold values of the NMOS and PMOS devices (L = 0.3 μm, W = 2.5 μm), as well as oscillation frequency of a 31 stage ring oscillator (0.35 μm gate, 0.7 μm contact size) fabricated on this run.

No.

Parameters

Units

NMOS

PMOS

1

Vt

V

0.53

- 0.52

2

Sub Threshold Slope

mV/decade

83

91

3

Ring oscillator frequency

(31 stages, 0.35μm gate, 3.3V)

MHz

114

 

 

 

(a)                                                                       (b)

Figure 1 -   a)  Drain Current vs. Drain Voltage Characteristics

                  b)  Subthreshold Voltage Characteristics of a 0.3 ΅m NMOS Device  ( L = 0.3 ΅m W = 2.5 ΅m)

 

(a)                                                                     (b)

Figure 2 -   (a) Drain Current vs. Drain Voltage Characteristics

                  (b) Subthreshold Voltage Characteristics of a 0.3 ΅m PMOS Device  ( L = 0.3 ΅m W = 2.5 ΅m)

VII.        REPORTS, PUBLICATION & TRAININGS

VIII.      FUTURE GOALS/WORK

Future Upgrade, Process Development & Support

 

MEMORANDUM

To:           Katalin Voros, Operations Manager

From:          Baseline group (Sia Parsa and Gyorgy Vida)

Subject:      Mix & Match process (ASML/GCAWS6 Steppers)

Date:          26 December 2006

Cc:             Bill Flounders, Microlab Technology Manager

                  Bob Hamilton, Microlab Facilities Manager

 

 

Abstract

A new Mix&Match process implemented on our 6" ASML/GCAWS6 steppers. This will enable members use both steppers on the same run, assigning the critical layers to the DUV ASML stepper, while non critical layers can be exposed on our i-line stepper, GCAWS6. New CAD templates and stepper jobs were released for this process.

Introduction

Mix&Match technique has long been used by the Micro-fabrication facilities to utilize their lithography equipment more efficiently, specifically the exposure tools. This is specially important in the dynamic world of semiconductor industry, where device sizes are on a shrinking path and the need for more advanced lithography equipment with better resolution/registration capability are an inherent part of the operation. By moving the critical layers onto more advance equipment and extending the life of existing older equipment for non-critical layers, companies could effectively reduce their capital investment/cost of operation. There are essentially two paths available for mix and matching layers on exposure tools, based on machine compatibility and the alignment schemes used by such tools.  The first method involves mix and matching of lithography layers on the same brand of exposure tools (steppers/scanners), which most likely use similar alignment schemes, i.e. ASML 2500, 5000 series and/or 5500 series. This is a much more straightforward task than a second method, which could involve different brands and/or generation of tools. This report focuses on the latter, involving the Microlab ASML 5500/90 and GCA8500 model steppers. These steppers use different alignment schemes, also print different maximum field sizes. This means the grid size/placement, wafer to chuck centering/positioning procedure, as well as the type of target used for the alignment scheme are different; all of which make the Mix&Match scheme more challenging.

Experimental Procedure

The Mix & Match procedure in the Microlab was developed and tested by printing two consecutive layers from the baseline CMOS-170 design layout on ASML and GCAWS6 steppers. Overlay performance (layer to layer registration) was evaluated between the contact layer, printed on the ASML, and next layer, metal -1 on the GCAWS6 stepper. The contact layer (1st layer) was printed/etched into a thin oxide film, followed by metal-1 printed/etched into a thin poly layer on top of the oxide. This provided sharper image/s for SEM inspection/overlay measurements. Test wafers were split at the metal-1 lithography step, where one group of wafers received  the global alignment (only), and the other group global alignment plus ΅-DFAS alignment on the GCASW6 stepper (Figure 1 in the Appendix), as per following steps:

1.       Printed/etched PM (pre-alignment) marks, zero layer on the ASML stepper, etched in lam5.

2.       Exposed the first layer (contact) on ASML stepper by aligning contact to PM marks (zero layer). Global alignment and ΅-DFAS (Dark Field Alignment) targets were also printed as part of the die in specific locations, as per GCAWS6 mask design specification. This was needed for GCAWS6 alignment (Global + ΅-DFAS) at metal-1 lithography step.

3.       Etched all wafers in Centura MxP+ etcher, contacts into the oxide layer.

4.       A thin layer of poly was then deposited on all wafers.

5.       Wafers were then split into two groups to evaluate global and global + ΅-DFAS alignment schemes on the GCAWS6 stepper.

6.       Metal -1 resist pattern was then transferred into the poly film by etching the samples in Lam5 etcher.

Note:    Once the PM (ASML alignment marks), global/΅-DFAS targets (GCAWS6 alignment targets) are etched into the substrate, all subsequent ASML and/or GCAWS6 layers could be aligned/exposed, as per standard ASML/GCA steppers procedure.  This means ASML layers would use the PM marks and GCA layers global and/or ΅-DFAS targets.

Unexpected Difficulties

1.       Wafer Rotation and X-Y Offsets

There is a mechanical stage difference between the ASML and the GCAWS6 steppers, which manifests itself as gross rotational and X-Y translational offset (mm range) on printed layers. This makes the job of locating global alignment targets very difficult, hence aligning GCAWS6 layer/s basically impractical for the Mix&Match process.  A good amount of effort was expended to find a viable method to compensate for this effect by first applying a wafer rotation (θ) at the ASML layer, then some X&Y translational offset in GCAWS6 job to bring the global targets within the GCAWS6's capturing range (joysticks). This basically forced the ASML exposure grid to match the GCAWS6's grid (please note, no wafer rotation feature is available on the GCAWS6 stepper). We experimented with ASML wafer rotation in the range of +2° to -2°, which later resulted in the best choice of θ  = +0.5°. Therefore, specific Mix&Match jobs on both the ASML (wafer rotation of θ  = +0.5°), and GCAWS6 (target key offset of X = 1.019 mm and Y = 0.5418 mm) were implemented, which brought the global targets within the capturing range of the GCAWS6 stepper, and the Metal -1 layer exposure possible.

2.       CAD layout Origin Mismatch

After the θ, X & Y adjustment noted in item #1 (above paragraph), we were able to print the GCAWS6 layer (global targets landed on the GCA screen), but the layers came out misaligned (micron range) in both X & Y directions. This sent us back to the drawing board and the investigation/redesign of the ASML/GCAWS6 templates used by our students to create their masks. The root cause of this problem was eventually determined as embedded grid offset in the ASML layout template that was provided to us by the ASML Company (Microlab standard template). This was not an issue as long as all layers were printed on the ASML stepper. GCAWS6 template on the other hand was developed in-house, and had its origin placed at (0,0). The GCAWS6 template was combined with the ASML template for the Mix&Match layers, and the offset (origin mismatch) still did not show at this point, not until masks were made and the layers printed on the steppers. After much experimentation with the CAD layout, we were able to correct the ASML template origin mismatch. New versions of ASML templates (Mix&Match versions) are now available for the Mix&Match process. Figure 2 in the Appendix displays the CAD layout of a 4-field ASML Mix&Match template. Members can drop their ASML layer design/s into the new ASML template/s (1 field or 4 field version), then import their GCAWS6 template/layers with no subsequent misalign problems at the lithography steps.

CAD Design

New ASML templates were developed to resolve X-Y translational error that would otherwise be introduced by the standard ASML (old) template for the Mix&Match case.

ASML stepper templates:     ASML_Mix_Match-1Q.gds (1 field, new/modified design)

                                          ASML_Mix_Match-4Q.gds (4 fields, new/modified design)

GCAWS6 template:             GCAWS6_templet1x.gds (old template, OK)

Stepper Job Set Ups

The fist and foremost challenging part of the Mix&Match set up involves placement accuracy of the exposure grid (fields), which ties into successful alignment target capturing and acceptable overlay registration for a particular layer. 

Results

The overlay results of the Mix&Match process was very good, in some cases better than vendor specification in the X and specially in Y directions (as long as the ΅-DFAS targets were used for GCA alignment). Registration accuracy is/was therefore, limited by the performance capability of the GCA stepper for the Mix& Match process. Other factors, such as; operator skill (how well global targets were aligned on the GCA stepper screen), stepper calibration, could also play a role in the overlay registration quality.  To minimize such effects, we performed ΅-DFAS baseline correction, before exposing our metal -1 layer, also assigned our most experienced staff on the job of aligning/exposing the GCAWS6 layer. Below are vendor's overlay specification and our measurement data from the SEM images shown in the Appendix  for the array and the transistor cells displayed in Figure 3 and Figure 4, respectively.

Vendor Specifications

ASML overlay accuracy defined by vendor:                       <  70 nm

GCAWS6 overlay accuracy defined by GCA vendor:          < 150 nm for  ΅-DFAS target

                                                                                    <  350 nm  global targets, only

Global Alignment, GCAWS6  (Wafers #4)

Large X&Y misalignments are shown on Figure 5 in the Appendix for the global alignment scheme, as calculated below. Global targets by themselves are not good enough for the Mix&Match process. Figure 6 shows SEM image of another structure on the same wafer, #4. The misalignment is so large in this case that the measurements were not made.  

Δ X  = Pa6 - Pa10 = 3299 nm - 733.6 nm   =1283 nm         (misalignment in X direction, Fig. 5)

                  2                         2

Δ Y  = Pa2 - Pa5 =  1627 nm -  137.5 nm   = 745 nm         (misalignment in Y direction, Fig. 5)

                  2                         2

΅-DFAS Alignment Scheme (Wafers#2):

Good alignment achieved by using ΅-DFAS targets incorporated in the ASML mask layout (etched contact layer) and GCAWS6 mask layout (metal -1 litho layer). Misalignment in Y direction (perpendicular to the wafer flat) was negligible, much below vendor's specification and Δ in X direction (parallel to wafer flat) satisfied GCAWS6 vendor specification at around 250nm. This value could easily be improved by applying a X offset (correction), hence claiming it has satisfied the vendor's specification. Please note, above noted vendor specification (΅-DFAS target scheme) applies to the case of all layers getting printed on the same stepper GCAWS6 (< 150nm).  See SEM images on Figures 7 and 8 for more detail.

Δ X  = Pa2 - Pa1 = 1236 nm - 847 nm   = 194 nm         (misalignment in X direction, Fig. 7)

                  2                         2

Δ Y  = Pa3 - Pa4 = 1351 nm - 1282 nm   = 34 nm         (misalignment in Y direction, Fig. 7)

                  2                         2

and,

Δ X  = Pa9 - Pa8 =  2335nm - 1786 nm   = 275 nm         (misalignment in X direction, Fig. 8)

                  2                         2

Δ Y  = Pa6 - Pa5 =  869.9 nm - 869.9 nm   ~  0 nm         (misalignment in Y direction, Fig. 8)

                  2                         2

Misalignment in Y direction was much below vendor specification on all images measured.

Conclusion & Future Work

Mix&Match process was successfully implemented on ASML/GCAWS6 steppers under the requirement that  ΅-DFAS target be used on GCA layers. This methodology can only be applied to new run/s. The most logical path for the best resolution and alignment result would be to keep critical layers on the ASML 5500/90 (DUV) stepper, while non-critical layers get addressed on the GCA (I-line) stepper. ASML and GCAWS6 templates are now available for CAD design, as well as pertinent jobs on the ASML/GCAWS6 steppers. Future work will involve mix and matching of the baseline layers on these two steppers for the proof of the concept at the 0.35 ΅m baseline process.

Acknowledgements

The baseline team would like to thank Noel Arellano for lending his GCAWS6 work wafer for initial ASML job set up/exposure grid matching, as well as his valuable input/help with testing the final layer on the GCAWS6 stepper. We would like to also thank Kim Chan and Marilyn Kushner for their assistance in exposing the GCAWS6 layer, SEM work and setting up the GCAWS6 Mix& Match job for this development work and the future member use.

Appendix

Figures & Schematics

 

Figure 1 –  Images of GCAWS6 Global Target (left) and ΅-DFAS Target/s (right)

Figure 2 – Four-Field Version of  the ASML Mix&Match Template

Note:  Added structures in red, allowed for the origin offset.

Figure 3 - SEM Image of a Memory Array on Wafer #2 – ΅-DFAS Alignment

Figure 4 - SEM Image of Transistor Cells on Wafer #2 – ΅-DFAS Alignment

Figure 5 – SEM Image of Wafer #4 – Global Alignment Only

Figure 6 – SEM Image of Wafer #4 – Global Alignment Only

Figure 7 – SEM Image of Wafer #2 – ΅-DFAS Alignment

Figure 8 – SEM Image of Wafer #2 – ΅-DFAS Alignment