6” (150 mm) Upgrade Timeline

1995	Discussion of upgrade need/plans at the 1^st and 2^nd Labnetwork meetings
1996	Incremental upgrade plan developed for 6” CMOS processing 3-phase plan presented at Labnetwork meeting in December – no funding model
1997	Funding plans: BMLA established Overhead on external user fees MEMS Exchange proposal (for higher rate of lab utilization) Equipment and material donation opportunities Research groups’ grant proposals to include 6”equipment
1998	Funding development: UC SMART grant (donated equipment value partially matched by grant) Intel donation (equipment & installation expenses) Facilities preparation: Rm 190
1999	Facilities preparation: Rm 144, GL4
2000	Mask making and lithography module completed PolySi/nitride etch Furnace bank3: all LPCVD, CMOS and MEMS
2001	Furnace bank1: atmospheric tubes, CMOS and MEMS CAPE – new computer LAN and software WIS – new equipment control hardware and software First 6” CMOS run started (1 μm process) 4” capability maintained: developed dual 4”/6” handling on etchers Measurement tools
2002	6” CMOS tools completed: First 6” CMOS run (CMOS 150 1µm techn.) completed, tested, report submitted New lab management software design started (Mercury) Utilities upgrades: New liquid nitrogen (LN) vessels Specialty gas storage New lab planning
2003	Operating manuals updated Web site updated MEMS-specific tools upgrade continuing Process development for 0.35 μm CMOS RUMS: facilities monitoring hardware, software New lab planning
2004	Additional wafer stepper, etching capability MEMS-specific tools upgrade completed 0.35 μm process completed, cmos 161 tested – high yield Final report on 6” upgrade New lab value engineering and redesign

Table 2

12/10/04