Benchmarking Semiconductor Manufacturing

A Research Program at the
University of California at Berkeley
Prof. Robert C. Leachman,
Prof. David A. Hodges,
Project Co-Directors


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Table of Contents

Benchmarking Semiconductor Manufacturing


CSM Program

CSM Program (cont.)

Purpose of This Study

Products of CSM Program

Research Dissemination

Benchmarking Progress

Factory Data Collection

Fab Categories

Memory Fab Line Yield

Memory Fab Defect Density, 0.7-0.9 micron

Memory Fab Integrated Yield, 0.45-0.6 micron

Memory Fab Integrated Yield, 0.7-0.9 micron

Memory Fab 5X Stepper Productivity

Memory Fab 5X Stepper Integrated Throughput

Memory Fab Cycle Time Per Layer

Memory Fab Direct Labor Productivity

Memory Fab Total Labor Productivity

CMOS Logic Fab Line Yield

CMOS Logic Fab Defect Density

CMOS Logic Fab Integrated Yield, 0.7-0.9 micron

CMOS Logic Fab Integrated 5X Stepper Throughput

CMOS Logic Fab Cycle Time Per Layer

CMOS Logic Fab Direct Labor Productivity

CMOS Logic Fab Total Labor Productivity

Site Visit

Site Visit (cont.)

“Externalities” in Performance

Determining Best Practices

Eight Basic Themes for Best Practices

Eight Themes (cont.)

Making manufacturing mistake-proof

Automation of information handling

Integrated data analysis

Developing a problem-solving organization

Technical talent

Reduced division of labor

Manage new process development and transfer


Technological improvements

Summary of major findings

Summary of findings

Summary of findings (cont.)

Organizational differences

Practices at U.S. firms vs. practices at leading Asian firms

Preliminary conclusions

Preliminary conclusions (cont.)

Important industry trends

Success of the fabless - foundry business model

Program plans

Authors: Rob Leachman, Dave Hodges